Dual Monochrome 8-Bit Panel Timing; Figure 7-20: Dual Monochrome 8-Bit Panel Timing - Epson S1D13704 Technical Manual

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7.3.8 Dual Monochrome 8-Bit Panel Timing

FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/02/08
LINE 1/241 LINE 2/242 LINE 3/243
1-1 1-5
1-2 1-6
1-3
1-7
1-4 1-8
241-1 241-5
241-2 241-6
*
241-3 241-7
241-4 241-8

Figure 7-20: Dual Monochrome 8-Bit Panel Timing

= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
VDP
LINE 4/244 LINE 239/479 LINE 240/480
HDP
VNDP
LINE 1/241 LINE 2/242
HNDP
1-637
1-638
1-639
1-640
241-637
241-638
241-639
241-640
S1D13704
X26A-A-001-04
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