Epson S1D13704 Technical Manual page 71

Embedded memory color lcd controller
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Epson Research and Development
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REG[13h] Screen 1 Vertical Size Register (LSB)
Address = FFF3h
Screen 1
Screen 1
Vertical Size
Vertical Size
Bit 7
Bit 6
REG[14h] Screen 1 Vertical Size Register (MSB)
Address = FFF4h
n/a
n/a
REG[14h] bits 1-0
REG[13h] bits 7-0
Hardware Functional Specification
Issue Date: 01/02/08
Screen 1
Screen 1
Vertical Size
Vertical Size
Bit 5
Bit 4
n/a
n/a
Screen 1 Vertical Size Bits [9:0]
This register is used to implement the Split Screen feature of the S1D13704. These bits
determine the height (in lines) of Screen 1. On reset this register is set to 0h.
In landscape modes, if this register is programmed with a value, n, where n is less than the
Vertical Panel Size (REG[06h], REG[05h]), then lines 0 to n of the panel contain Screen 1
and lines n+1 to REG[06h], REG[05h] of the panel contain Screen 2. See Figure 8-1:
"Screen-Register Relationship, Split Screen," on page 64. If Split Screen is not desired,
this register must be programmed greater than, or equal to the Vertical Panel Size,
REG[06h] and REG[05h].
In SwivelView modes this register must be programmed greater than, or equal to the Verti-
cal Panel Size, REG[06h] and REG[05h]. See "SwivelView™" on page 79.
Screen 1
Screen 1
Vertical Size
Vertical Size
Bit 3
Bit 2
n/a
n/a
*
Page 63
Read/Write
Screen 1
Screen 1
Vertical Size
Vertical Size
Bit 1
Bit 0
Read/Write
Screen 1
Screen 1
Vertical Size
Vertical Size
Bit 9
Bit 8
S1D13704
X26A-A-001-04

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