Table 7-2: Sh-3 Bus Timing - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f
Bus Clock frequency
CKIO
T
Bus Clock period
CKIO
t2
Clock pulse width high
t3
Clock pulse width low
t4
A[15:0], RD/WR# setup to CKIO
t5
A[15:0], RD/WR# hold from CS#
t6
BS# setup
t7
BS# hold
t8
CSn# setup
t9
Falling edge RD# to DB[15:0] driven
t10
Rising edge CSn# to WAIT# high impedance
t11
Falling edge CSn# to WAIT# driven
t12
CKIO to WAIT# delay
t13
DB[15:0] setup to 2
t14
DB[15:0] hold from rising edge of WEn# (write cycle)
t15
DB[15:0] valid to RDY# falling edge setup time (read cycle)
t16
Rising edge RD# to DB[15:0] high impedance (read cycle)
Note
Hardware Functional Specification
Issue Date: 01/02/08

Table 7-2: SH-3 Bus Timing

Parameter
nd
CKIO after BS# (write cycle)
a
One Software WAIT State Required
CKIO may be turned off (held low) between accesses - see Section 13.5, "Turning Off
BCLK Between Accesses" on page 86
Min
0
1/f
CKIO
17
16
0
0
5
5
0
0
0
0
*
a
Max Units
50 MHz
ns
ns
ns
ns
ns
ns
ns
25 ns
10 ns
15 ns
20 ns
ns
ns
ns
10 ns
S1D13704
X26A-A-001-04
Page 29