Epson S1D13704 Technical Manual page 409

Epson Research and Development
Vancouver Design Center
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4-1: Typical Implementation of an 8-bit Processor to the S1D13704 Generic #2 Interface . . 11
Interfacing to an 8-bit Processor
Issue Date: 01/02/12
List of Tables
List of Figures
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S1D13704
X26A-G-013-02