Epson S1D13704 Technical Manual page 308

Page 12
S1D13704
X26A-G-008-05
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
face for Generic #2 mode. However, BS# is used to configure the S1D13704 for
Generic #2 mode and should be tied high (connected to IO V
be tied high.
*
Interfacing to the NEC VR4102™ Microprocessor
Epson Research and Development
Vancouver Design Center
). RD/WR# should also
DD
Issue Date: 01/02/12