Burst Cycles - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center
SIZ[1:0], TT[1:0]
SIZ[1:0], TT[1:0]

2.1.3 Burst Cycles

Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 01/02/12
BCLK0
TS
TA
TIP
A[31:0]
R/W
D[31:0]
Transfer Start Wait States
Figure 2-1: MCF5307 Memory Read Cycle
BCLK0
TS
TA
TIP
A[31:0]
R/W
D[31:0]
Transfer Start
Figure 2-2: MCF5307 Memory Write Cycle
Burst cycles are very similar to normal cycles, except that they occur as a series of four
back-to-back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output
asserted continuously through the burst. Burst memory cycles are mainly intended to facil-
itate cache line fill from program or data memory; they are typically not used for transfers
to or from IO peripheral devices such as the S1D13704. The MCF5307 chip selects provide
a mechanism to disable burst accesses for peripheral devices which are not able to support
them.
Transfer
Complete
*
Valid
Wait States Transfer
Complete
Sampled when TA low
Next Transfer
Starts
Next Transfer
Starts
Page 9
S1D13704
X26A-G-011-03