Direct Connection To The Philips Pr31500/Pr31700; General Description - Epson S1D13704 Technical Manual

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2 Direct Connection to the Philips PR31500/PR31700

2.1 General Description

PR31500/PR31700
/RD
/WE
/CARD1CSL
/CARD1CSH
ENDIAN
ALE
A[12:0]
D[31:24]
D[23:16]
/CARD1WAIT
DCLKOUT
S1D13704
X26A-G-012-02
In this example implementation the S1D13704 occupies the PR31500/PR31700 PC Card slot #1.
The S1D13704 is easily interfaced to the PR31500/PR31700 with minimal additional logic. The
address bus of the PR31500/PR31700 PC Card interface is multiplexed and can be demultiplexed
using an advanced CMOS latch (e.g., 74ACT373). The direct connection approach makes use of the
S1D13704 in its "Generic Interface #2" configuration.
The following diagram demonstrates a typical implementation of the interface.
Latch
V
DD
pull-up
Clock divider
Figure 2-1: S1D13704 to PR31500/PR31700 Direct Connection
The "Generic #2" host interface control signals of the S1D13704 are asynchronous with respect to
the S1D13704 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13704 clock frequencies.
The S1D13704 also has internal clock dividers providing additional flexibility.
+3.3V
IO V
DD
IO V
DD
System RESET
*
See text
...or...
Oscillator
Interfacing to the Philips MIPS PR31500/PR31700 Processor
EPSON Research and Development
Vancouver Design Center
S1D13704
IO V , CORE V
DD DD
RD#
WE#
BHE#
BS#
RD/WR#
RESET#
CS#
AB[15:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
CLKI
BCLK
Issue Date: 01/02/12