Generic #1 Host Bus Interface Mode - Epson S1D13704 Technical Manual

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3.2 Generic #1 Host Bus Interface Mode

S1D13704
X26A-G-010-03
Two other configuration options (CNF[4:3]) are also made at time of hardware reset:
• endian mode setting (big endian or little endian).
• polarity of the LCDPWR signal.
The capability to select the endian mode independent of the host bus interface offers more
flexibility in configuring the S1D13704 with other CPUs.
For details on configuration, refer to the S1D13704 Hardware Functional Specification,
document number X26A-A-001-xx.
Generic #1 host bus interface mode is the most general and least processor-specific host bus
interface mode on the S1D13704. The Generic # 1 host bus interface mode was chosen for
this interface due to the simplicity of its timing.
The host bus interface requires the following signals:
• BUSCLK is a clock input which is required by the S1D13704 host interface. It is sepa-
rate from the input clock (CLKI) and is typically driven by the host CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is writing data to the S1D13704. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is reading data from the S1D13704. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• WAIT# is a signal output from the S1D13704 that indicates the host CPU must wait
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the S1D13704 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the S1D13704 internal registers and/or refresh
memory. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. This signal is active low and may need to be inverted if
the host CPU wait state signal is active high.
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode.
However, BS# is used to configure the S1D13704 for Generic #1 mode and should be
tied low (connected to GND).
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Interfacing to the Motorola MPC821 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/12