Epson S1D13704 Technical Manual page 61

Epson Research and Development
Vancouver Design Center
Symbol
Shift Pulse period
t1
Shift Pulse pulse width high
t2
Shift Pulse pulse width low
t3
Data setup to Shift Pulse falling edge
t4
Data hold from Shift Pulse falling edge
t5
Line Pulse cycle time
t6
Line Pulse pulse width low
t7
t8 Frame Pulse cycle time
t9 Frame Pulse pulse width low
t10 Horizontal display period
t11 Line Pulse setup to Shift Pulse falling edge
Frame Pulse falling edge to Line Pulse falling
t12
edge phase difference
t13 DRDY to Shift Pulse falling edge setup time
t14 DRDY pulse width
t15 DRDY falling edge to Line Pulse falling edge
t16 DRDY hold from Shift Pulse falling edge
t17 Line Pulse Falling edge to DRDY active
1. Ts = pixel clock period
2. t6min = [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0)+4) x 8] Ts
3. t8 min = [((REG[06h] bits 1-0, REG[05h] bits 7-0)+1) + (REG[0Ah] bits 6-0)] Lines
4. t10min = [((REG[04h] bits 6-0)+1) x 8] Ts
5. t14min = [((REG[04h] bits 6-0)+1) x 8] Ts
6. t15min = [(REG[07h] bits 4-0) x 8 + 16] Ts
7. t17min = [(REG[08h] bits 4-0) - (REG[07]) x 8 + 16] Ts
Hardware Functional Specification
Issue Date: 01/02/08
Parameter
*
Min Typ
1
0.5
0.5
0.5
0.5
note 2
9
note 3
2t6
note 4
0.5
t6 - 18Ts
0.5
note 5
note 6
0.5
note 7
Page 53
Max Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
250
S1D13704
X26A-A-001-04