Epson S1D13704 Technical Manual page 173

Embedded memory color lcd controller
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Epson Research and Development
Vancouver Design Center
** Copyright (c) 1998 Epson Research and Development, Inc.
** All Rights Reserved.
**---------------------------------------------------------------------------
**
** The data in this file was generated using 1374CFG.EXE.
**
** The configureation parameters chosen were:
**
320x240 Single Color 8-bit STN (format 2)
**
4 bpp - 70 Hz Frame Rate (25 MHz CLKi)
**
High Performance enabled
**
**===========================================================================
*/
/**************************************************************/
/*
1374 HAL HDR
/*
HAL_STRUCT Information generated by 1374CFG.EXE
/*
Copyright (c) 1998 Seiko Epson Corp. All rights reserved. */
/*
/*
Include this file ONCE in your primary source file
/**************************************************************/
HAL_STRUCT HalInfo =
{
"1374 HAL EXE",
0x1234,
sizeof(HAL_STRUCT), /* Size
0x00,
0x23,
0xB0,
0x1E,
0x00,
0x3B,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
25000,
0xD0000,
70,
};
/*--------------------------------------------------------------------------*/
/*
**===========================================================================
**
HAL_REGS.H
**---------------------------------------------------------------------------
**
Created 1998, Epson Research & Development
**
**
Copyright(c) Seiko Epson Corp. 1998.
**===========================================================================
*/
#ifndef __HAL_REGS_H__
#define __HAL_REGS_H__
/*
Programming Notes and Examples
Issue Date: 01/02/12
(do not remove)
/* ID string
/* Detect Endian */
0x03,
0x27,
0x00,
0x00,
0xFF,
0x03,
0x00,
0x00,
Vancouver Design Center.
*/
*
*/
0xEF,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
/* ClkI (kHz)
/* Display Address */
** Panel Frame Rate (Hz) */
All rights reserved.
Page 77
*/
*/
*/
*/
*/
S1D13704
X26A-G-002-03

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