Motorola M68K #1 Interface Timing; Table 7-3: M68K #1 Bus Timing (Mc68000); Figure 7-3: M68K #1 Bus Timing (Mc68000) - Epson S1D13704 Technical Manual

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7.1.3 Motorola M68K #1 Interface Timing

CLK
A[15:1]
CS#
R/W#
AS#
UDS#, LDS#
DTACK#
D[15:0]
(write
D[15:0]
(read)
Symbol
f Bus Clock Frequency
CLK
T Bus Clock period
CLK
t1 A[15:1], CS# valid before AS# falling edge
t2 A[15:1], CS# hold from AS# rising edge
t3 AS# low to DTACK# driven high
t4 CLK to DTACK# low
t5 AS# high to DTACK# high
t6 AS# high to DTACK# high impedance
t7 UDS#, LDS# falling edge to D[15:0] valid (write cycle)
t8 D[15:0] hold from AS# rising edge (write cycle)
t9 UDS#, LDS# falling edge to D[15:0] driven (read cycle)
t10 D[15:0] valid to DTACK# falling edge (read cycle)
t11 UDS#, LDS# rising edge to D[15:0] high impedance
S1D13704
X26A-A-001-04
T
CLK
t1
INVALID
t3
Hi-Z
Hi-Z
t9
Hi-Z

Figure 7-3: M68K #1 Bus Timing (MC68000)

Table 7-3: M68K #1 Bus Timing (MC68000)

Parameter
Note
CLK may be turned off (held low) between accesses - see Section 13.5, "Turning Off
BCLK Between Accesses" on page 86
VALID
t4
t7
VALID
t10
VALID
*
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t2
t6
t5
Hi-Z
t8
Hi-Z
t11
Hi-Z
Min Max Units
0 33 MHz
1/f
CLK
0 ns
0 ns
16 ns
15 ns
20 ns
T
CLK
T
CLK
0 ns
15 ns
0 ns
10 ns
Hardware Functional Specification
Issue Date: 01/02/08