Rom Flash And Memory Interface Signals - LSI LSI53C875A Technical Manual

3.6 ROM Flash and Memory Interface Signals

Table 3.12

ROM Flash and Memory Interface Signals

Name PQFP
MWE/ 139
MCE/ 141
MOE/ 140
MAC/_ 77
TESTOUT
MAS0/ 137
MAS1/ 136
Table 3.12 describes the ROM Flash and Memory Interface signals.
BGA Type Strength Description
C7 O 4 mA
A7 O 4 mA
B7 O 4 mA
L10 O 16 mA
A8 O 4 mA
B8 O 4 mA
ROM Flash and Memory Interface Signals
Memory Write Enable. This pin is used as a write
enable signal to an external flash memory.
Memory Chip Enable. This pin is used as a chip
enable signal to an external EEPROM or flash
memory device.
Memory Output Enable. This pin is used as an
output enable signal to an external EEPROM or
flash memory during read operations. It is also
used to test the connectivity of the LSI53C875A
signals in test mode.
Memory Access Control. This pin can be
programmed to indicate local or system memory
accessed (non-PCI applications). It is also used to
test the connectivity of the LSI53C875A signals in
test mode.
Memory Address Strobe 0. This pin is used to
latch in the least significant address byte (bits [7:0])
of an external EEPROM or flash memory. Since
the LSI53C875A moves addresses eight bits at a
time, this pin connects to the clock of an external
bank of flip-flops which are used to assemble up to
a 20-bit address for the external memory.
Memory Address Strobe 1. This pin is used to
latch in the most significant address byte (bits
[15:8]) of an external EEPROM or flash memory.
Since the LSI53C875A moves addresses eight bits
at a time, this pin connects to the clock of an
external bank of flip-flops which assemble up to a
20-bit address for the external memory.
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