Bit Operating Register/Scripts Ram Read - LSI LSI53C875A Technical Manual

Table 6.17

32-Bit Operating Register/SCRIPTS RAM Read

Symbol Parameter
t Shared signal input setup time
1
t Shared signal input hold time
2
t CLK to shared signal output valid
3
Figure 6.11 32-Bit Operating Register/SCRIPTS RAM Read
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD
(Driven by Master-Addr;
LSI53C875A-Data)
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C875A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
t
1
t
2
Addr
In
t
2
t
1
CMD
t
2
t
1
In
t
2
t
1
t
3
PCI and External Memory Interface Timing Diagrams
Min
Byte Enable
t
3
Max
7 –
0 –
– 11
t
3
Data
Out
t
2
t
3
Out
t
2
Unit
ns
ns
ns
6-15