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12.4
Reset
Reset of UART should be held to an idle mode reset high for 500ns until initialization, which
causes the following:
1. Initialization of the transmitter and receiver internal clock counters.
2. Resetting all bits of ULSR, (except ULSR(5) and ULSR(6), THRE and TEMT (they are set
only by a hardware reset), all bits of UMCR and all corresponding discrete lines, memory and
logic elements. Before resetting, UART remains in the idle mode until programmed.
Table 12.7 Reset Control of Register and Pinout Signals
Register/Signal
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
SOUT
RTS#, DTR#
Reset Control
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset Status
All bits Low
Bit 0 is high and bits 1-7 are low
All bits Low
All bits Low
All bits Low
Bits 5, 6 are high, others are low.
Bits 7-4 input signals, bits 0-3 low
High
High
Rev. 3.0, 03/01, page 167 of 390
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