Hitachi HD64465 User Manual page 17

Figure 5-3. Low-Speed Internal Peripheral Bus Access Timing With TWe Phase......................46
Figure 5-4. High-Speed Basic Internal Peripheral Bus Access Timing .......................................47
Figure 5-5. High-Speed Internal Peripheral Bus Access Timing With TWe Phase .....................48
Figure 6-1. AFECK Related Clock Diagram ...............................................................................59
Figure 6-2. UCK Related Clock Diagram ....................................................................................60
Figure 6-3. System Hardware Reset Related Pins........................................................................65
Figure 6-4. Power-On Reset Diagram, tPORST=10ms................................................................65
Figure 6-5. SH4 Manual Reset Diagram, tM2PS=tM2PH=80ns, tMARST=10ms......................66
Figure 6-6. SH3 Manual Reset Diagram, tMARST=10ms ..........................................................66
Figure 7-1. Pin Configuration of All Ports...................................................................................70
Figure 8-1. Block Diagram of the Interrupt Controller ................................................................80
Figure 9-1. Block Diagram of Timer ...........................................................................................90
Figure 9-2. Interrupt Request Timer1/0r Timing Diagram in Case Prescale *1,
Timer1/0_clk=CKIO ..............................................................................................105
Figure 9-3. Interrupt Request Timer1/0r Timing Diagram in Case Prescale*1/4,
Timer1/0_clk = CKIO/4 .........................................................................................105
Figure 9-4. Interrupt Request Timer1/0r Timing Diagram in Case Prescale*1/8,
Timer1/0_clk = CKIO/8 .........................................................................................106
Figure 9-5. Interrupt Request Timer1/0r Timing Diagram in Case Prescale*1/16,
Timer1/0_clk = CKIO/16 .......................................................................................106
Figure 9-6. A/D Trigger Signal ADTRIG# Timing Diagram in Case Prescale 1,
Timer0_clk=CKIO..................................................................................................107
Figure 9-7. A/D Trigger Signal ADTRIG# Timing Diagram in Case Prescale 1/4,
Timer0_clk=CKIO/4 ..............................................................................................107
Figure 9-8. A/D Trigger Signal ADTRIG# Timing Diagram in Case Prescale 1/8,
Timer0_clk=CKIO/8 ..............................................................................................107
Figure 9-9. A/D Trigger Signal ADTRIG# Timing Diagram in Case Prescale 1/16,
Timer0_clk=CKIO/16 ............................................................................................107
Figure 9-10. PWM Signals...........................................................................................................108
Figure 11-1. Functional Block Diagram of FIR ...........................................................................130
Figure 14-1. The Block Diagram of Serial CODEC Interface .....................................................182
Figure 14-2. Data Transfer Scheme in DMA TX Mode ..............................................................219
Figure 14-3. CS4218 or CS4271 TX Controller ..........................................................................220
Figure 14-4. CS4218 or CS4271 RX Controller ..........................................................................220
Figure 14-5. AC97 TX Controller................................................................................................221
Figure 14-6. AC97 RX Controller ...............................................................................................222
Figure 14-7. TX Flow in PIO Mode for CS4218 or CS4271 .......................................................223
Figure 14-8. RX Flow in PIO Mode for CS4218 or CS4271 .......................................................224
Figure 14-9. AC97 DMA Program Flow .....................................................................................225
Figure 14-10. Warm/Cold Reset Timing......................................................................................226
Figure 14-11. Serial Data Setup, Hold and Output Delay Timing ...............................................226
Figure 15-1. AFE Interface Block Diagram.................................................................................230
Figure 15-2. Divider Configuration .............................................................................................239
Rev. 3.0, 03/01, page xi of xiii