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14.2.2 Receive Data Register (RDR) ..............................................................................185
14.2.3 Control Register (CR) ..........................................................................................186
14.2.4 Status Register (SR) .............................................................................................187
14.2.5 Frequency Select Register ....................................................................................189
14.2.6 Command/Status Address Register (CSAR) ........................................................190
14.2.7 Command/Status Data Register (CSDR)..............................................................191
14.2.8 PCM Playback/Record Left Channel (PCML).....................................................192
14.2.9 PCM Playback/Record Right Channel (PCMR) ..................................................193
14.2.10 Line 1 Data Register (LINE1) ..............................................................................194
14.2.11 PCM Center Playback/MIC ADC Channel (PCMC) ...........................................195
14.2.12 PCM Left Surround Channel Data Register (PCMLS) ........................................196
14.2.13 PCM Right Surround Channel Data Register (PCMRS) ......................................197
14.2.14 PCMLFE Data Register (PCMLFE) ....................................................................198
14.2.15 Line 2 Channel Data Register (LINE2)................................................................199
14.2.16 HSET Data Register (HSET) ...............................................................................200
14.2.17 IO Control/Status Data Register (IOCS) ..............................................................201
14.2.18 AC97 Transmit Interrupt Enable Register (ATIER) ............................................202
14.2.19 AC97 TX FIFO Status Register ...........................................................................205
14.2.20 AC97 RX FIFO Interrupt Enable Register (ARIER) ...........................................208
14.2.21 AC97 RX Status Register (ARSR).......................................................................211
14.2.22 AC97 Control Register (ACR) .............................................................................213
14.2.23 AC97 TAG Register (ATAGR)............................................................................215
14.2.24 Slot Request Active Register (SRAR)..................................................................216
14.3 Function Description .........................................................................................................217
14.3.1 Internal Bus Interface ...........................................................................................217
14.3.2 Clock Generator ...................................................................................................217
14.3.3 CS4218 or CS4271 TX Controller .......................................................................218
14.3.4 CS4218 or CS4271 RX Controller .......................................................................218
14.3.5 AC97 TX Controller.............................................................................................218
14.3.6 AC97 RX Controller ............................................................................................219
14.3.7 Miscellaneous Function Block .............................................................................219
14.3.8 Data Structure of Memory in DMA Mode ...........................................................219
14.4 Program Flow....................................................................................................................220
Section 15 AFE Interface ..................................................................................229
15.1 Overview ...........................................................................................................................229
15.1.1 Features ................................................................................................................229
15.1.2 Block Diagram .....................................................................................................230
15.2 Register Description ..........................................................................................................231
15.2.1 Control Register (CTR) ........................................................................................232
15.2.2 Status Register (STR)...........................................................................................233
15.2.3 Transmit Data Register (TXDR) ..........................................................................236
15.2.4 Receive Data Register (RXDR)............................................................................236
Rev. 3.0, 03/01, page v of xiii
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