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(2) UMSR (READ/WRITE)
This 8-bit register provides current state of the control lines from modems or peripheral devices. In
addition to this current state information; bits 7~ 4 can provide change information when a modem
control input changes state. It will be reset to low when the Host reads the UMSR.
Bit
Description
7
Data Carrier Detect (DCD#): Indicates the complement status of Data Carrier Detect
input. If bit 4 of UMCR is 1, this bit is equivalent to OUT2 of the UMCR.
6
Ring Indicator (RI#): Indicates the complement to the RI# input. If bit 4 of UMCR is 1, this
bit is equivalent to OUT1 in the UMCR.
5
Data Set Ready (DSR#): Indicates the modem is ready to provide received data to the
serial channel receiver circuitry. If the serial channel is in the loop mode (bit 5 of UMCR is
1), this bit is equivalent to DTR# in the UMCR.
4
Clear to Send (CTS#): Indicates the complement of CTS# input. If the serial channel is in
the loop mode (bit 4 of UMCR is 1), this bit is equivalent to RTS# in the UMCR.
3
Delta Data Carrier Detect (DDCD): Indicates that the DCD# input state has been
changed since the last time read by the Host.
2
Trailing Edge of Ring Indicator (TERI): Indicates that the RI input state to the serial
channel has been changed from a low to high since the last time read by the Host. The
change to logic 1 doesn't activate the TERI.
1
Delta Data Set Ready (DDSR): A logic "1" indicates that the DSR# input to the serial
channel has changed state since the last time it was read by the Host.
0
Delta Clear to Send (DCTS): This bit indicates that the CTS# input state to the serial
channel has been changed since the last time it was read by the Host
Table 12.6 Modem Status Register Bits
Bit
Mnemonic
7
DCD#
6
RI#
5
DSR#
4
CTS#
3
DDCD
2
TERI
1
DDSR
0
DCTS
Rev. 3.0, 03/01, page 166 of 390
Logic 0
Data Carrier Detect
Ring Indicator
Data Set Ready
Clear To Send
Delta Data Carrier Detect
Trailing Edge of Ring Indicator
Delta Data Set Ready
Delta Clear to Send
Default
-
-
-
-
-
-
-
-
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