Figure 18.6 Endpoint Descriptor - Hitachi HD64465 User Manual

5) Description Registers
The ED Block maintains 4 32-bit registers to hold requested Endpoint Descriptors. These
registers are used as temporary storage for Endpoint Descriptors being serviced and are not
addressable by software. Figure 18-6 shows the fields present in each of the 4 Endpoint
Descriptor registers.
3
1
Dword 0 —
Dword 1
TD Queue Tail Pointer (TailP)
Dword 2
TD Queue Head Pointer (HeadP)
Dword 3
Next Endpoint Descriptor (NextED)
Please refer to the OpenHCI specification for details on particular field names and functions.
TD Block
The TD Block is responsible for processing Transfer Descriptors. This is the bulk of the work
performed by the Host Controller. This block is responsible for reading Transfer Descriptors from
memory, requesting transactions when appropriate, writing back status, and retiring TDs when
necessary (including the management of the Done Queue).
2
6
MPS

Figure 18.6 Endpoint Descriptor

1 1 1 1 1 1 1
6 5 4 3 2 1 0
F K S D
EN
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0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
FA
—
0 C H
—