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Table 13-3. Status Port Register Description ...............................................................................173
Table 13-4. Control Port Register Description.............................................................................173
Table 13-5. Bit Map of the ECP Mode Register ..........................................................................174
Table 13-6. ECP Register Definition ...........................................................................................175
Table 13-7. ECP Mode Description .............................................................................................175
Table 14-1. Pin Function of Serial CODEC Interface Module ....................................................183
Table 14-2. Registers of SCDI .....................................................................................................183
Table 14-3. AC97 Timing ............................................................................................................227
Table 15-1. Pin Function of AFE Interface Module ....................................................................231
Table 15-2. Registers of AFE Interface .......................................................................................231
Table 16-1. Pin Function of Keyboard Controller Interface Module ...........................................235
Table 16-2. Keyboard Controller Interface Read Cycle AC Timing ...........................................248
Table 16-3. Keyboard Controller Interface Write Cycle AC Timing...........................................248
Table 17-1. PS/2 Interface Control Registers...............................................................................249
Table 17-2. Data Receive Timing Parameters..............................................................................257
Table 17-3. Data Send Timing Parameters ..................................................................................258
Table 18-1. Example Calculation of R and Host Controller Action ............................................275
Table 18-2. ITD Packet Offset Location ......................................................................................276
Table 18-3. Completion Codes ....................................................................................................279
Table 18-4. Dword0 GTD Fields .................................................................................................282
Table 18-5. Dword0 ITD Fields...................................................................................................282
Table 18-6. Dword1 GTD Fields .................................................................................................282
Table 18-7. Dword1 ITD Fields...................................................................................................283
Table 18-8. Dword2 Fields ..........................................................................................................283
Table 18-9. Dword3 GTD Fields .................................................................................................283
Table 18-10. Dword3 ITD Fields.................................................................................................283
Table 18-11. Offset0 Field Description........................................................................................284
Table 18-12. List Processor Control Signals................................................................................285
Table 18-13. Transaction Control Information ............................................................................294
Table 18-14. PID Encoding..........................................................................................................295
Table 18-15. Bus Time-out Periods .............................................................................................305
Table 18-16. SIE EOF Timing Requirements ..............................................................................306
Table 18-17. SIE Completion Status............................................................................................308
Table 18-18. IN Transaction Error Response...............................................................................309
Table 18-19. OUT Transaction Error Response...........................................................................309
Table 18-20. Hub / Port Commands.............................................................................................310
Table 18-21. Power Switching Configurations ............................................................................311
Table 18-22. HC Operational Register Summary ........................................................................316
Table 18-23. HcRevision Register ...............................................................................................317
Table 18-24. HcControl Register .................................................................................................318
Table 18-25. HcCommandStatus Register ...................................................................................319
Table 18-26. HcInterruptStatus Register......................................................................................320
Table 18-27. HcInterrutpEnable Register ....................................................................................321
Rev. 3.0, 03/01, page ix of xiii
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