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Page Crossing Controller
The Page Crossing Controller is responsible for controlling the page address of data transfers. If it
receives a request from the Data Buffer Engine that crosses a page boundary, it will break up the
request into two separate requests to the Bus Master Controller. The first request will contain the
data from the first page, the second request will contain the data from the second page.
The Page Crossing Controller is also responsible for indicating to the Bus Master Controller to
load the page address of the second page into the upper 20 bits of the address register. This occurs
whenever the address increments to the next page, either due to a page crossing or the current
request ends at the end of a page.
Data Buffer (DB)
The Data Buffer serves as the data interface between the PCI Controller and the SIE. It is a
combination of a 64-byte latched based bi-directional asynchronous FIFO and a single Dword PCI
Holding Register.
The PCI Holding Register is a 32-bit edge-triggered register that is used for two purposes: First, to
serve as a data pipeline stage so that the PCI control signal TRDY# can be synchronized before
going into the write enable logic of the latches in the Data Buffer. Second, to serve as a holding
register for the last Dword of an OUT transfer that won? fit into the FIFO. This is required for
General Transfer Descriptors since the entire data packet, up to 64 bytes, must be read entirely into
the buffer before the data request begins. Depending on the begin address of the packet, there could
be up to 17 Dwords to be stored.
The Data Buffer maintains the number of bytes transferred for the current data packet. This value
is used by the List Processor to update the status of the Transfer Descriptor.
The number of bytes transferred is compared with the expected number of bytes to produce a last
byte flag when the values are equal. The SIE uses the last byte flag for two purposes: First, to
determine if the current IN packet is a data overrun or data underrun. Second, to indicate that there
are no more bytes for the current OUT packet. The Data Buffer also uses the last byte flag to
inhibit any data beyond the expected size for an IN packet from being stored in the buffer
18.2.3
USB Interface
The USB interface includes the integrated Root Hub with two external ports, Port 1 and Port 2 as
well as the Serial Interface Engine (SIE) and USB clock generator. The interface combines
responsibility for executing bus transactions requested by the HC as well as the hub and port
management specified by USB.
Rev. 3.0, 03/01, page 293 of 390
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