Figure 18.14 Crc Logic - Hitachi HD64465 User Manual

1) Data
Data fields of the token packets are provided by the List Processor and Frame Manager. For a
transmitted data packet, the Data Buffer Engine provides the data. Each time a byte is loaded
into the shifter the buffer pointer is incremented. The data buffer marks the data byte enabling
the CRC remainder into the data stream.
If the data buffer experiences an underrun condition such that the data packet cannot be
completed, the Serializer will immediately force a bit stuff error followed by the EOP.
For a received data packet, the data is provided to the data buffer after each byte. A latch holds
each byte while a new byte is collected. The latch is necessary to allow synchronization be the
PCI clock domain of the data buffer and the USB clock domain of the receiver. When the EOP
is detected the last two bytes sent to the data buffer are invalidated as the two CRC bytes.
These bytes can only be identified after the fact.
2) CRC Generator/Checker
The CRC is calculated using a generator polynomial applied to a data pattern. The data pattern
includes all data fields excluding sync patterns, PIDs, and data bytes sans the NRZI encoding.
Below is a description of the CRC procedure. See also Figure 18-14.
 At the start of the packet, preload 1 into the CRC remainder registers (5 bits for token, 16
bits for data).
 The next data bit is XORed with the MSb of the remainder and left shifted (to MSb) filling
with 0.
 If the XOR result was 1 the generator polynomial is XORed with the remainder during the
shift. (The LSb of the remainder is the fill 0).
At the end of the data pattern the remainder is inverted and transmitted at the tail of the packet,
MSb first.
token
0015h
1 DataBit
8005h
0
Rev. 3.0, 03/01, page 300 of 390
shift
crc_en
1
1
0 1
0
0
FFFFh
crc[15:0]
{ crc[14:0], 1'b0 }

Figure 18.14 CRC Logic

token
crc[4]
CRC
crc[15]
Remainder
crc[15:0]
800Dh
1
crc_out
0
crc_check