Internal Bus Data Swap Rules - Hitachi HD64465 User Manual

5.5

Internal Bus Data Swap Rules

Internal Bus Data Swap Rules are defined to satisfy the legacy peripheral modules. This is
because the data bus width has been changed from 16 bits to 32 bits. For the compliance with these
legacy peripheral modules, it is required to establish a data swap mechanism described below:
Case 1: Word Access (16 bits)
IMADDR[1]=0 CPU Bus
Write Enable WE3#
Value H
Data Position X
IMADDR[1]=1 CPU Bus
Write Enable WE3#
Value L
Data Position byte3
Case 2: Double Word Access (32 bits)
IMADDR[1]=0 CPU Bus
Write Enable WE3#
Value L
Data Position byte3
WE2# WE1# WE0#
H L L
x Byte1 byte0
WE2# WE1# WE0#
L H H
byte2 x x
WE2# WE1# WE0#
L L L
byte2 Byte1 byte0
Internal Bus
IMWE3# IMWE2# IMWE1# IMWE0#
H H L
x x byte1
Internal Bus
IMWE3# IMWE2# IMWE1# IMWE0#
H H L
x x byte3
Internal Bus
IMWE3# IMWE2# IMWE1# IMWE0#
L L L
byte3 byte2 byte1
Rev. 3.0, 03/01, page 49 of 390
L
byte0
L
byte2
L
byte0