Control Registers: Uier, Uiir, Ufcr, Udll, Udlm, Ulcr, Umcr - Hitachi HD64465 User Manual

12.3.2

Control Registers: UIER, UIIR, UFCR, UDLL, UDLM, ULCR, UMCR

(1) UIER (READ/WRITE)
UIER is used to enable (or disable) four active high interrupts that activate the interrupt outputs,
with its lower four bits: bit 0~bit 3.
Bit Description
7 - 4 These bits are always "0".
3 Sets this bit high to enable the Modem Status Interrupt when one of the Modem Status
Registers changes its bit state.
2 Sets this bit high to enable the Receiver Line Status Interrupt, which is caused when
Overrun, Parity, Framing or Break occurs.
1 Sets this bit high to enable the Transmitter Holding Register Empty Interrupt.
0 Sets this bit high to enable the Received Data Available Interrupt (and Time-out Interrupt
in the FIFO mode).
(2) UIIR (READ only)
This register facilitates the host CPU to determine interrupt priority and its source. The priority of
four existing interrupt levels is as follows:
1. Received Line Status (highest priority)
2. Received Data Ready
3. Transmitter Holding Register Empty
4. Modem Status (lowest priority)
When a privileged interrupt is pending and the type of interrupt is stored in the UIIR which is
accessed by the Host, the serial channel holds back all interrupts and indicates the highest priority
pending interrupts to the Host. Any new interrupts will not be acknowledged until the Host access
finishes. The contents of the UIIR are described in the table on the next page.
Rev. 3.0, 03/01, page 159 of 390
Default
0
0
0
0
0