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(2) Master Status Register (IMSTSR)
Address: H'10007102 (Bank 0, Read)
Bit
7
Bit Name
-
Initial Value
-
R/W
-
Bit
Description
7
Reserved
6
Timer Interrupt (TMI)
When set to 1, indicates a timer interrupt is pending.
5
Transmitter Interrupt (TXI)
When set to 1, indicates a transmitter interrupt is pending.
4
Receiver Interrupt (RXI)
When set to 1, indicates a receiver interrupt is pending. The following conditions clear the
Rx interrupt condition.
•
Reading the Rx Ring Frame Counter Low Register
•
Issuing a RESET, Rx SPECIAL CONDITION INTERRUPT command
•
Clearing the Rx Enable bit
•
HARDWARE REST
•
SOFTWARE RESET
Interrupt identification (IID[2:0])
3 - 1
These three bits correspond to interrupt identification ID2 - ID0 which provide an
alternative method for identifying the interrupt source by indicating the interrupt type and
priority level as shown below:
Interrupt Type
Rx Special Condition
1. FIFO Overrun
2. Frame Error
3. EOF
4. Rx Abort
5. Sync/Hunt
Rx Data Available
Tx Buffer Empty
Tx Special Condition
1. FIFO Underrun
2. EOM
3. Early EOM
0
Reserved
6
5
4
TMI
TXI
RXI
0
0
0
R
R
R
ID2
ID1
ID0
1
0
0
1
0
1
1
1
0
1
1
1
3
2
IID2
IID1
0
0
R
R
Priority
Highest
Second
Third
Fourth
Rev. 3.0, 03/01, page 135 of 390
1
0
IID0
-
0
-
R
-
Default
-
-
-
-
-
-
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