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3.1
Overview
Exception handling is performed in the H8/3637 Series when a reset or interrupt occurs.
Table 3.1 shows the priorities of these two types of exception handling.
Table 3.1
Exception Handling Types and Priorities
Priority
Exception Source
High
Reset
Interrupt
Low
3.2
Reset
3.2.1
Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-
chip peripheral modules are initialized.
3.2.2
Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the H8/3637 Series enters the reset
state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• When an external clock or ceramic oscillator is used, also, at power on the RES pin must be
held low for the crystal oscillator oscillation stabilization time shown in table 14.3 in section
14, Electrical Characteristics.
• Resetting during operation: Hold the RES pin low for at least 18 system clock cycles.
Reset exception handling begins when the RES pin is held low for a given period, then returned to
the high level. Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
Section 3 Exception Handling
Time of Start of Exception Handling
Exception handling starts as soon as the reset state is cleared
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling
in progress is completed
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