Port Interrupt Control Register - Hitachi HD64465 User Manual

7.3.3

Port Interrupt Control Register

This register is used to enable or disable to generate the interrupt request when an interrupt event is
triggered on each I/O port pin. An interrupt request is generated when an interrupt event is
triggered and its corresponding register bit is set to "1". But the Interrupt request will not be
generated if its corresponding control register bit is "0," despite that the interrupt event is triggered.
This register can independently select the trigger edge of the interrupt events on each I/O port pin.
GPAICR -- Address: H'10004020
Bit 15
Bit Name PA7TS
Initial Value 0
R/W R/W
Bit 7
Bit Name PA7IM
Initial Value 1
R/W R/W
GPBICR -- Address: H'10004022
Bit 15
Bit Name PB7TS
Initial Value 0
R/W R/W
Bit 7
Bit Name PB7IM
Initial Value 1
R/W R/W
GPCICR -- Address: H'10004024
Bit 15
Bit Name PC7TS
Initial Value 0
R/W R/W
Rev. 3.0, 03/01, page 74 of 390
14 13 12
PA6TS PA5TS PA4TS
0 0 0
R/W R/W R/W
6 5 4
PA6IM PA5IM PA4IM
1 1 1
R/W R/W R/W
14 13 12
PB6TS PB5TS PB4TS
0 0 0
R/W R/W R/W
6 5 4
PB6IM PB5IM PB4IM
1 1 1
R/W R/W R/W
14 13 12
PC6TS PC5TS PC4TS
0 0 0
R/W R/W R/W
11 10 9
PA3TS PA2TS PA1TS
0 0 0
R/W R/W R/W
3 2 1
PA3IM PA2IM PA1IM
1 1 1
R/W R/W R/W
11 10 9
PB3TS PB2TS PB1TS
0 0 0
R/W R/W R/W
3 2 1
PB3IM PB2IM PB1IM
1 1 1
R/W R/W R/W
11 10 9
PC3TS PC2TS PC1TS
0 0 0
R/W R/W R/W
8
PA0TS
0
R/W
0
PA0IM
1
R/W
8
PB0TS
0
R/W
0
PB0IM
1
R/W
8
PC0TS
0
R/W