Table 18.26 Hcinterruptstatus Register - Hitachi HD64465 User Manual

HcInterruptStatus
All bits are set by hardware and cleared by software.

Table 18.26 HcInterruptStatus Register

Register: HcInterruptStatus
Bits Reset
31 0h
30 0b
29 - 7 0h
6 0b
5 0b
4 0b
3 0b
2 0b
1 0b
0 0b
Rev. 3.0, 03/01, page 320 of 390
Offset: 0C-0F
R/W Description
- Reserved. Read/Write 0's
R/W OwnershipChange
This bit is set when the OwnershipChangeRequest bit of
HcCommandStatus is set.
- Reserved. Read/Write 0's
R/W RootHubStatusChange
This bit is set when the content of HcRhStatus or the content of
any HcRhPortStatus register has changed.
R/W FrameNumberOverflow
This bit is set when bit 15 of FrameNumber changes value
from '0' to '1' or from '1' to '0.'
R UnrecoverableError
This event is not implemented and is hard-coded to '0.' All
writes are ignored.
R/W ResumeDetected
This bit is set when the Host Controller detects resume
signaling on a downstream port.
R/W StartOfFrame
This bit is set when the Frame Management block signals a
?tart of Frame' event.
R/W WritebackDoneHead
This bit is set after the Host Controller has written HcDoneHead
to HccaDoneHead.
R/W SchedulingOverrun
This bit is set when the List Processor determines a Schedule
Overrun has occurred.