Table 12.3 Baud Rates Using (9.216Mhz/5) Clock - Hitachi HD64465 User Manual

Table 12.3 Baud Rates Using (9.216MHz/5) Clock

Desired Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
(6) ULCR (READ/WRITE)
ULCR controls the format of the data character and gives the information of the serial line.
Bit Description
7 Divisor Latch Access Bit: Must be set high to access the Divisor Latches of the baud
rate generator during read or write operations. It must be set low to access the Data
Register (URBR and UTBR) or the Interrupt Enable Register.
6 Break Control: Forces the Serial Output (SOUT) to the spacing state (logic 0) by a logic
1, and this state will remain until a low level resetting ULCR(6), enabling the serial port to
alert the terminal in a communication system.
5 Stick Parity Bit: When this bit and ULCR(3) are high at the same time, the parity bit is
transmitted and then detected by receiver, in opposite state by ULCR(4) to force the parity
to a known state and to check the parity bit in a known state.
4 Even Parity Select (EPS): When parity is enabled (ULCR(3)=1), ULCR(4)=0 selects odd
parity, and ULCR(4)=1 selects even parity.
Rev. 3.0, 03/01, page 162 of 390
Divisor Used
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
Default
-
-
-
-