System Configuration Register (Sconfr) - Hitachi HD64465 User Manual

6.3.2

System Configuration Register (SCONFR)

This register provides a flexible approach for system configuration. The hardware wait insertion
control is flexible to control CPU interface command cycle. Parallel Port function select can also
be programmed by this register. The detailed functionality, which can be configured, is described
below:
Address: H'10000002
Bit 15
Bit Name -
Initial Value 0
R/W R
Bit 7
Bit Name -
Initial Value 0
R/W R
Bit Description
15 - 14 Reserved.
13 SLS: System Low Speed Select. This bit is used to select the low speed or high-speed
timing according to different bus clock (CKIO) rates.
When this bit is set to 1, the low speed timing is selected in internal bus.
When this bit is cleared to 0, the high-speed timing is selected in internal bus.
For CKIO, - 25MHz, low speed is recommended.
For CKIO, 25 – 66MHz, high speed is recommended.
12 HWEN: CPU interface Hardware Wait Number Enable. This bit is used to enable the wait
cycles of HW[3:0]. When this bit is set, the CPU interface will insert the hardware wait
cycles as the HW[3:0] programmed. If this bit is cleared, the CPU interface will not insert
any hardware wait cycles.
11 - 8 HW[3:0]: CPU interface Hardware Wait Number Control. The number of HW[3:0] stands
for the cycles of hardware wait state inserted. The inserted cycles start at the second
software wait state. This wait number is effective only after the HWEN has been set. The
wait cycle can be any one number from 1 to 15. Note that the relationship between
HW[3:0] and CPU programmed inserted wait states (IWS) is 2 ≤ IWS ≤ 1 + HW[3:0].
Hence, the CPU default inserted wait states should be 2.
7 - 6 Reserved.
Rev. 3.0, 03/01, page 54 of 390
14 13 12
- SLS HWEN
0 0 1
R R/W R/W
6 5 4
- USBCKS SCDICKS PPFMS1 PPFMS0 KBWUP -
0 0 0
R R/W R/W
11 10 9
HW3 HW2 HW1
0 0 0
R/W R/W R/W
3 2 1
0 0 0
R/W R/W R/W
8
HW0
1
R/W
0
0
R
Default
0
1
0001
0