Hitachi HD64465 User Manual page 305

Windows ce intelligent peripheral controller
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Frame Management
The frame management block is responsible for managing the frame specific tasks required by the
USB specification and the OpenHCI specification. These tasks are:
1. Management of the OpenHCI frame specific Operational Registers
2. Operation of the Largest Data Packet Counter
3. Performing frame qualifications on USB Transaction requests to the SIE
4. Generate SOF token requests to the SIE
Operational Registers
The Host Controller uses four registers to perform the frame timing and status tasks of frame
management. These registers are HcFmInterval, HcFmRemaining, HcFmNumber, HcLSThreshold,
and HcPeriodicStart. The function and operation of each register is detailed below.
1) HcFmlnterval Register
The HcFmInterval register contains three fields. These fields are FrameInterval,
FrameIntervalToggle, and FSLargestDataPacket.
The FrameInterval field specifies the length of a frame in USB bit times and is programmed
by the HCD. FrameInterval and FrameIntervalToggle are loaded into the FrameRemaining
counter and FrameRemainingToggle, respectively, at the beginning of each frame. When
programming FrameInterval, the FrameIntervalToggle field is toggled by the HCD each
time a new interval is specific. The HCD uses the FrameIntervalToggle and
FrameRemainingToggle fields to see when the Host Controller has started using a newly
programmed FrameInterval value (see discussion below).
The FSLargestDataPacket field specifies a value which is loaded into the Largest Data Packet
Counter at the beginning of each frame. (See next section for a discussion of this function) This
field is programmed by the HCD.
2) HcFmRemaining Register
The HcFmRemaining register contains two fields, FrameRemaining and
FrameRemainingToggle.
The FrameRemaining field is a 14-bit counter. When operating, the counter value decrements
once per USB bit time. The FrameRemaining counter is valid only when the Host Controller
is in the U
O
SB
PERATIONAL
with the value of FrameInterval at the next rising edge of the 12 MHz reference clock. In
addition, the counter will load with FrameInterval when the Host Controller transitions into
the U
O
SB
PERATIONAL
Rev. 3.0, 03/01, page 286 of 390
state. When FrameRemaining reaches a value of 0, it is loaded
state to re-initialize the frame period.

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