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AC97 Transmit Interrupt Enable Register (ATIER) [cont'd]
Bit
Description
15
PCMLS TX FIFO OVERRUN Interrupt Enable (PLSTFOVIE):
When this bit is 1, PCMLS TX FIFO OVERRUN Interrupt is enabled.
When this bit is 0, PCMLS TX FIFO OVERRUN Interrupt is disabled.
14
PCMRS TX FIFO OVERRUN Interrupt Enable (PRSTFOVIE):
When this bit is 1, PCMRS TX FIFO OVERRUN Interrupt is enabled.
When this bit is 0, PCMRS TX FIFO OVERRUN Interrupt is disabled.
13
PCMLFE TX FIFO OVERRUN Interrupt Enable (PLFETFOVIE):
When this bit is 1, PCMLFE TX FIFO OVERRUN Interrupt is enabled.
When this bit is 0, PCMLFE TX FIFO OVERRUN Interrupt is disabled.
Line2 TX FIFO OVERRUN Interrupt Enable (L2TFOVIE):
12
When this bit is 1, Line 2 TX FIFO OVERRUN Interrupt is enabled.
When this bit is 0, Line 2 TX FIFO OVERRUN Interrupt is disabled.
HSET TX FIFO OVERRUN Interrupt Enable (HTTFOVIE):
11
When this bit is 1, HSET TX FIFO OVERRUN Interrupt is enabled.
When this bit is 0, HSET TX FIFO OVERRUN Interrupt is disabled.
10
IO CTRL TX FIFO OVERRUN Interrupt Enable (IOCTFOVIE):
When this bit is 1, IO CTRL TX FIFO OVERRUN Interrupt is enabled.
When this bit is 0, IO CTRL TX FIFO OVERRUN Interrupt is disabled.
9
PCML TX FIFO UNDERRUN Interrupt Enable (PLTFUNIE):
When this bit is 1, PCML TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, PCML TX FIFO UNDERRUN Interrupt is disabled.
8
PCMR TX FIFO UNDERRUN Interrupt Enable (PRTFUNIE):
When this bit is 1, PCMR TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, PCMR TX FIFO UNDERRUN Interrupt is disabled.
7
Line 1 TX FIFO UNDERRUN Interrupt Enable (L1TFUNIE):
When this bit is 1, Line 1 TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, Line 1 TX FIFO UNDERRUN Interrupt is disabled.
6
PCMC TX FIFO UNDERRUN Interrupt Enable (PCTFUNIE):
When this bit is 1, PCMC TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, PCMC TX FIFO UNDERRUN Interrupt is disabled.
5
PCMLS TX FIFO UNDERRUN Interrupt Enable (PLSTFUNIE):
When this bit is 1, PCMLS TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, PCMLS TX FIFO UNDERRUN Interrupt is disabled.
4
PCMRS TX FIFO UNDERRUN Interrupt Enable (PRSTFUNIE):
When this bit is 1, PCMRS TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, PCMRS TX FIFO UNDERRUN Interrupt is disabled.
Rev. 3.0, 03/01, page 204 of 390
Default
0
0
0
0
0
0
0
0
0
0
0
0
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