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6.3.5
System Peripheral S/W Reset Control Register (SPSRCR)
The software reset of each peripheral module is an option when the peripheral module encounters
functional failures after clearing the STANDBY mode of the module. These software reset bits
need the clock from UCK oscillator to count the reset period, which means that the UCKOSC bit
needs to be cleared first before setting these reset bits. Note that multiple bits can be set at the same
time. But during the reset period, no other bits can be set until all the bits, which have been set, are
cleared.
Address: H'10000008
Bit
15
Bit Name
SPORST PS2SRT -
Initial Value
1
R/W
R
Bit
7
Bit Name
USBSRT PC0SRT PC1SRT AFESRT TM0SRT
Initial Value
0
R/W
R/W
Bit
Description
15
SPORST: System Power-On Reset. When this bit is set, the system power-on reset is
going. At this time, the whole chip is still in reset state after H/W reset. All R/W accesses
must wait for this bit to clear to zero. Note this register is readable during system power-
on reset state.
14
PS2SRT: PS2 Controller Software Reset. When this bit is set, the PS2
Controller will be reset. This reset is equivalent to hardware reset. All the PS2
Controller registers are set to the reset default values. Note that the software reset bit is
self-clearing.
13
Reserved.
12
ADCSRT: A/D Controller Software Reset. When this bit is set, the A/D controller will be
reset. This reset is equivalent to hardware reset. All the A/D controller registers are set to
the reset default values. Note that the software reset bit is self-clearing.
11
UARTSRT: UART Controller Software Reset. When this bit is set, the UART will be reset.
This reset is equivalent to hardware reset. All the UART registers are set to the reset
default values. Note that the software reset bit is self-clearing.
10
Reserved
9
SCDISRT: Serial Codec Controller Software Reset. When this bit is set, the SCDI will be
reset. This reset is equivalent to hardware reset. All the SCDI registers are set to the reset
default values. Note that the software reset bit is self-clearing.
14
13
12
ADCSRT UARTSRT -
0
0
0
R/W
R
R/W
6
5
4
0
0
0
R/W
R/W
R/W
11
10
0
0
R/W
R
3
2
TM1SRT IRDASRT KBCSRT
0
0
R/w
R/W
Rev. 3.0, 03/01, page 61 of 390
9
8
SCDISRT PPSRT
0
0
R/W
R/W
1
0
0
0
R/W
R/W
Default
1
0
0
0
0
0
0
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