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10.4.10 PCC1 Card Status Change Interrupt Enable Register (PCC1CSCIER)................125
10.4.11 PCC1 Software Control Register (PCC1SCR) .....................................................127
Section 11 FIR Module ..................................................................................... 129
11.1 Overview ...........................................................................................................................129
11.1.1 Features ................................................................................................................129
11.1.2 Functional Block Diagram of FIR........................................................................130
11.2 FIR Controller Register Description..................................................................................132
11.2.1 UART Register of FIR Portion ............................................................................132
11.2.2 FIR Controller Register ........................................................................................133
11.2.3 Register Description .............................................................................................134
11.3 FIR Transmit Operation ....................................................................................................153
11.4 FIR Receive Operation ......................................................................................................154
11.5 Example of Initialization and Programming Procedure for HP-SIR .................................156
Section 12 UART .............................................................................................. 157
12.1 Overview ...........................................................................................................................157
12.2 Features .............................................................................................................................157
12.3 Serial Channel Register Description..................................................................................158
12.3.1 Data Register ........................................................................................................158
12.3.3 Status Register ULSR and UMSR........................................................................164
12.4 Reset ..................................................................................................................................167
12.5 Programming.....................................................................................................................168
12.5.1 Programming Sequence........................................................................................168
12.6 Software Reset...................................................................................................................168
12.7 Clock Input Operation .......................................................................................................168
12.8 FIFO Interrupt Mode Operation ........................................................................................169
12.9 CAUTION.........................................................................................................................170
Section 13 Parallel Port ..................................................................................... 171
13.1 Overview ...........................................................................................................................171
13.2 Features .............................................................................................................................171
13.3 Parallel Port Register Description .....................................................................................171
13.3.1 SPP and EPP Modes.............................................................................................173
13.3.2 ECP Mode ............................................................................................................174
Section 14 Serial CODEC Interface.................................................................. 181
14.1 Overview ...........................................................................................................................181
14.1.1 Features ................................................................................................................181
14.1.2 Block Diagram .....................................................................................................182
14.2 Register Description ..........................................................................................................183
14.2.1 Transmit Data Register (TDR) .............................................................................184
Rev. 3.0, 03/01, page iv of xiii
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