Figure 6.1 Afeck Related Clock Diagram - Hitachi HD64465 User Manual

Peripheral Clock Relationship Diagrams shows the working relationship among the clock
source and generated peripheral clocks. It also indicates the sequence of turning off one peripheral
clock without interfering the other peripheral clocks operation. For example, in Figure 6-1, If the
bit AFEOSC is set, then peripheral clocks like AFE_clk and SCDI_clk will be halted because the
source clock AFECK is halted. To stop the AFE_clk, users can set the bit AFECLK in the system
peripheral clock control register (SPCCR). To turn on the AFE_clk again from the halted
condition, just let the bit AFECLK be cleared, AFE_clk will then start to run.
Follow the steps below to save power consumption:
1. Set bits AFECLK and SCDICLK to turn off AFE_clk and SCDI_clk (under SCDICKS=0).
This will reduce the power consumption of AFE and SCDI modules.
2. Even more power consumption can be saved on PLL1 if users set the bit AFEOSC.
Conversely, to make the peripheral clocks AFE_clk and SCDI_clk (under SCDICKS=0) to run
from AFEOSC bit, which has been set, users are required to follow the steps described below:
1. Clear AFEOSC, then wait about t
2. Clear AFECLK and SCDICLK to open the clock gating.
After these two steps, the peripheral clocks will start to run normally.
12.288Mhz
AFECK
AFEOSC
ms to allow PLL1 operate normally.
PLL
PLL1
x3
Frequency divider
x(1/4)
Frequency divider
x(1/3)
From Figure 2.

Figure 6.1 AFECK Related Clock Diagram

36.8Mhz
Clock
Gating
9.2Mhz
Control
AFECLK
12.288Mhz
Mux
12Mhz
SCDICLK
SCDICKS
Rev. 3.0, 03/01, page 59 of 390
AFE_clk
Clock
Gating
SCDI_clk
Control
ACCLK