Table of Contents
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5.4
Signal Timing Description ................................................................................................45
5.4.1
Low Speed Timing ...............................................................................................45
5.4.2
High Speed Timing ..............................................................................................47
5.5
Internal Bus Data Swap Rules...........................................................................................49
5.6
Internal Peripheral Bus AC Timing Specification.............................................................50
Section 6
Power Management and System Configuration.............................. 51
6.1
Overview ...........................................................................................................................51
6.2
Features .............................................................................................................................51
6.3
Register Description ..........................................................................................................52
6.3.1
System Module Standby Control Register (SMSCR) ..........................................52
6.3.2
System Configuration Register (SCONFR) .........................................................54
6.3.3
System Bus Control Register (SBCR)..................................................................55
6.3.4
System Peripheral Clock Control Register (SPCCR)...........................................57
6.3.5
System Peripheral S/W Reset Control Register (SPSRCR) .................................61
6.3.6
System PLL Control Register (SPLLCR) ............................................................63
6.3.7
System Revision Register (SRR)..........................................................................64
6.3.8
System Device ID Register (SDID) .....................................................................64
6.4
System Hardware Reset Timing ........................................................................................65
6.4.1
Power-On Reset Output .......................................................................................65
6.4.2
Manual Reset Output............................................................................................66
Section 7
General Purpose I/O Port ................................................................ 67
7.1
Overview ...........................................................................................................................67
7.1.1
Features ................................................................................................................67
7.2
Register Configuration ......................................................................................................69
7.3
Register Descriptions ........................................................................................................70
7.3.1
Port Data Register ................................................................................................70
7.3.2
Port Control Register............................................................................................72
7.3.3
Port Interrupt Control Register.............................................................................74
7.3.4
Port Interrupt Status Register ...............................................................................76
Section 8
Interrupt Controller (INTC) ............................................................ 79
8.1
Overview ...........................................................................................................................79
8.1.1
Features ................................................................................................................79
8.1.2
Block Diagram .....................................................................................................80
8.1.3
Pin Configuration .................................................................................................80
8.1.4
Register Configuration .........................................................................................80
8.2
Interrupt Sources ...............................................................................................................81
8.2.1
On-Chip Module Interrupt ...................................................................................81
8.2.2
Interrupt Exception Processing and Priority.........................................................81
8.3
NIRR: Interrupt Request Register .....................................................................................82
8.4
NIMR: Interrupt Mask Register ........................................................................................84
Rev. 3.0, 03/01, page ii of xiii
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