Table 18.24 Hccontrol Register - Hitachi HD64465 User Manual

HcControl

Table 18.24 HcControl Register

Register: HcControl
Bits Reset
31 - 11 0h
10 0b
9 0b
8 0b
7 - 6 00b
5 0b
4 0b
3 0b
Rev. 3.0, 03/01, page 318 of 390
Offset: 04-07
R/W Description
- Reserved. Read/Write 0's
R/W RemoteWakeupConnectedEnable
If a remote wakeup signal is supported, this bit is used to
enable that operation. Since there is no remote wakeup signal
supported, this bit is ignored.
R RemoteWakeupConnected
This bit indicated whether the HC supports a remote wakeup
signal. This implementation does not support any such signal.
The bit is hard-coded to '0.'
R/W InterruptRouting
This bit is used for interrupt routing:
0: Interrupts routed to normal interrupt mechanism (INT).
1: Interrupts routed to SMI.
R/W HostControllerFunctionalState
This field is used to set the Host Controller state. The state
encodings are:
00: U R
SB
01: U R
SB
10: U O
SB
11: U S
SB
The Host Controller may force a state change from
U S
SB USPEND
from a downstream port.
R/W BulkListEnable
When set this bit enables processing of the Bulk list.
R/W ControlListEnable
When set this bit enables processing of the Control list.
R/W IsochronousEnable
When clear, this bit disables the Isochronous List when the
Periodic List is enabled (so Interrupt EDs may be serviced).
While processing the Periodic List, the Host Controller will
check this bit when it finds an isochronous ED.
ESET
ESUME
PERATIONAL
USPEND
to U R after detecting resume signaling
SB ESUME