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15.2.3
Transmit Data Register (TXDR)
TXDR, a 16-bit READ/WRITE register, is used to transmit the stored data. All the bits in this
register are initialized to 0 at RESET. TXDR is not initialized in the STANDBY mode.
Bit
15
14
13
RESET 0
0
0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TXDR functions as a transmit data register when the BUFD bit (bit 15) in CTR is 1, and an AFE
control data transmit register when the BUFD bit is 0. (see Figure 15.1 on page 175)
15.2.4
Receive Data Register (RXDR)
RXDR, a 16-bit READ only register, is used to receive the stored data. All the bits in this register
are initialized to 0 at RESET. RXDR is not initialized in the STANDBY mode.
Bit
15
14
13
RESET 0
0
0
R/W
R
R
R
RXDR functions as a receive data register when the BUFD bit (bit 15) in CTR is 1, and an AFC
control data receive register when the BUFD bit is 0. AFE control data are stored and transmitted
to TXDR at the same time.
15.2.5
Transmit Data Buffers (TXDB0,1)
TXDB0 and TXDB1 act as transmit data storage buffers, and are able to store 48-word data. The
hardware configuration determines the buffer, from which the data are transmitted. A hardware
configuration determines which buffer data will be transmitted. Users can access only one buffer,
which is not currently used for data transmit. TDB0 and TDB1 are not initialized in the
STANDBY mode.
15.2.6
Transmit Shift Register (TSFTR)
TSFTR, a 16-bit register, is used to convert a parallel transmit data into a serial one. Note that
READ/WRITE operations cannot be performed to this register. The initial value of this register is
undefined at RESET or in the STANDBY mode.
Rev. 3.0, 03/01, page 236 of 390
12
11
10
9
0
0
0
0
12
11
10
9
0
0
0
0
R
R
R
R
8
7
6
5
0
0
0
0
8
7
6
5
0
0
0
0
R
R
R
R
4
3
2
1
0
0
0
0
4
3
2
1
0
0
0
0
R
R
R
R
0
0
0
0
R
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