Interrupt; Figure 15.4 Tdei Output Timing - Hitachi HD64465 User Manual

15.6

Interrupt

An AFE interface is capable of generating five interrupts. Among these interrupts, four interrupts
of TDEI, RDFI, TERI, and RERI are issued by setting the enable bits in CTR to 1. On the other
hand, an interrupt of RDWT is masked by setting the RDETM bit to 1.
Interrupt
Source Issuance Condition
TDEI Transmit register or buffer includes no transmit data.
RDFI Receive register or buffer is full of received data.
TERI Next data transmit starts while no transmit data is
included.
RERI Receive register or buffer receives the next data in
spite of being in the full status.
RDET When a low level is input to the RING pin (this is a
level interrupt).
Figures 15-4 and 15-5 shown below display the output timings of TDEI and RDFI.
For timings of TERI and RERI, TERI is output when the last word data transmission starts while
RERI is output when the last word data transmission is completed. When the BUFD bit is set to 1,
transmission is performed in 1 word, but output timings do not differ from those of TDEI and
RDFI.
FS
DIN
(TxD)
TDEI
data1 data2

Figure 15.4 TDEI Output Timing

How to clear the interrupt
Clear the TDE bit in STR
Clear the RDF bit in STR
Clear the TERR bit in STR
Clear the RERR bit in STR
Write 1 to the RSW bit in CTR
data47 data48
Rev. 3.0, 03/01, page 241 of 390