Serial Channel Register Description; Data Register; Table 12.1 Serial Channel Registers - Hitachi HD64465 User Manual

12.3

Serial Channel Register Description

Table 12.1 Serial Channel Registers

Register DLAB* Address
Data 0 Base+h0000
Control 0 Base+h0002
X Base+h0004
X Base+h0006
X Base+h0008
1 Base+h0000
1 Base+h0002
Status X Base+h000A
X Base+h000C
X Base+h000E
Notes: 1. DLAB* is bit 7 of the Line Control Register.
2. UART0 base address = H'10008000
12.3.1

Data Register

UTBR and URBR each hold from five to eight data bits. If the transmitted data is less than eight
bits, it aligns to the LSB. Either received or transmitted data is buffered by a shift register and is
latched first by a holding register. The bit 0 of any word is first received and transmitted.
(1) URBR (READ only)
This register receives and holds the entering data. It contains a non-accessible shift register which
converts the incoming serial data stream to a parallel 8 bit word.
(2) UTBR (WRITE only)
This register holds and transmits the data via a non-accessible shift register. It converts the
outgoing parallel data to a serial stream before transmission.
Rev. 3.0, 03/01, page 158 of 390
READ
URBR (Receiver Buffer Register)
UIER (Interrupt Enable Register)
UIIR (Interrupt identification Register)
ULCR (Line Control Register)
UMCR (Modem Control Register)
UDLL (Divisor Latch LSB)
UDLM (Divisor Latch MSB)
ULSR (Line Status Register)
UMSR ( Modem Status Register)
USCR (Scratch Pad Register)
WRITE
UTBR (Transmitter Buffer Register)
UIER
UFCR (FIFO Control Register)
ULCR
UMCR
UDLL
UDLM
ULSR
UMSR
USCR