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AC97 RX Status Register (ARSR) [cont'd]
Bit
Description
19
PCMR RX FIFO REQUEST (PRRFRQ):
When this bit is set to 1, it indicates that half of PCMR RX FIFO is full and must be cleared
by the system.
18
Line 1 RX FIFO REQUEST (L1RFRQ):
When this bit is set to 1, it indicates that half of Line 1 RX FIFO is full and must cleared by
the system.
17
MIC RX FIFO REQUEST (MICRFRQ):
When this bit is set to 1, it indicates that half of MIC RX FIFO is full and must be cleared
by the system.
16
Line2 RX FIFO REQUEST (L2RFRQ):
When this bit is set to 1, it indicates that half of Line 2 RX FIFO is full and must be cleared
by the system.
15
HSET RX FIFO REQUEST (HTRFRQ):
When this bit is set to 1, it indicates that half of HSET RX FIFO is full and must be cleared
by the system.
14
IO CTRL/Status RX FIFO REQUEST (IOCSRFRQ):
When this bit is set to 1, it indicates that half of IO CTRL/Status RX FIFO is full and must
be cleared by the system.
13
PCML RX FIFO OVERRUN (PLRFOV):
When this bit is set to 1, it indicates that PCML RX FIFO is overrun.
12
PCMR RX FIFO OVERRUN (PRRFOV):
When this bit is set to 1, it indicates that PCMR RX FIFO is overrun.
11
Line 1 RX FIFO OVERRUN (L1RFOV):
When this bit is se to 1, it indicates that Line 1 RX FIFO is overrun.
MIC RX FIFO OVERRUN (MICRFOV):
10
When this bit is set to 1, it indicates that MIC RX FIFO is overrun.
9
Line2 RX FIFO OVERRUN (L2RFOV):
When this bit is set to 1, it indicates that Line 2 RX FIFO is overrun.
8
HSET RX FIFO OVERRUN (HTRFOV):
When this bit is set to 1, it indicates that HSET RX FIFO is overrun.
7
IO CTRL/Status RX FIFO OVERRUN (IOCSRFOV):
When this bit is set to 1, it indicates that IO CTRL/Status RX FIFO is overrun.
6
PCML RX FIFO UNDERRUN (PLRFUN):
When this bit is set to 1, it indicates that PCML RX FIFO is underrun.
5
PCMR RX FIFO UNDERRUN (PRRFUN):
When this bit is set to 1, it indicates that PCMR RX FIFO is underrun
4
Line1 RX FIFO UNDERRUN (L1RFUN):
When this bit is set to 1, it indicates that Line 1 RX FIFO is underrun
3
MIC RX FIFO UNDERRUN (MICRFUN):
When this bit is set to 1, it indicates that MIC RX FIFO is underrun
Rev. 3.0, 03/01, page 212 of 390
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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