Ecp Mode; Table 13.5 Bit Map Of The Ecp Mode Register - Hitachi HD64465 User Manual

(5) EPP Data Port 0 - 3
The EPP Data Port 0 - 3 are only available in EPP mode. When the host writes to these ports, the
contents of D0 - D7 are buffered and output to PD0 - PD7 as an EPP DATA Write cycle. When the
host reads from these ports, the contents of PD0 - PD7 are buffered and output to D0-D7, and
causes an EPP DATA Read Cycle.
13.3.2

ECP Mode

This mode is both software and hardware compatible with that of the existing parallel ports,
allowing ECP to be used as a standard LPT port when ECP is not required. It provides an
automatic high-burst-bandwidth channel that supports ECP in both forward and reverse directions.
A 16-byte FIFO is implemented in both forward and reverse directions to smooth data flow and
improve the maximum bandwidth requirement. The port supports an automatic handshaking for the
standard parallel port to improve compatibility and increase the speed of mode transfer. It also
supports run-length encoded (RLE) decompression in hardware. Compression is accomplished by
counting identical bytes and transmitting an RLE byte that indicates how many times a byte is
repeated.

Table 13.5 Bit Map of the ECP Mode Register

Register D7
data PD7
ecpAFifo Addr/RLE Address or RLE field
dsr nBusy
dcr 1
cFifo Parallel Port Data FIFO
ecpDFifo ECP Data FIFO
tFifo Test FIFO
cnfgA 0
cnfgB 0
ecr mode
Rev. 3.0, 03/01, page 174 of 390
D6 D5
PD6 PD5
nAck PError
1 PDDIR
0 0
intrValue 0
D4 D3
PD4 PD3
Select nFault
IRQE SelectIn nInit
1 0
0 0
nErrIntrEn
D2 D1
PD2 PD1
1 1
AutoFd
0 0
0 0
ServiceIntr full
D0
PD0
1
Strobe
0
0
empty