Table of Contents
Advertisement
AC97 Control Register (ACR) [cont'd]
Bit
Description
31
Version Select (VS): If this bit is set to 1, this module supports AC97 Ver2.0. Otherwise,
this module supports AC97 Ver1.03
30 - 21
Reserved
22
RX DMA Enable (RXDMA_EN): If this bit is set to 1, RX DMA function is enabled.
Otherwise, RX DMA function is disabled.
21
TX DMA Enable (TXDMA_EN): If this bit is set to 1, TX DMA function is enabled.
Otherwise, TX DMA function is disabled.
20
Flush CAR FIFO (FCAF): When this bit is written by 1, command address FIFO is
flushed.
19
Flush CDR FIFO (FCDF): When this bit is written by 1, command data FIFO is flushed.
18
Flush STA FIFO (FSTAF): When this bit is written by 1, status address FIFO is flushed.
17
Flush STD FIFO (FSTDF): When this bit is written by 1, status data FIFO is flushed.
16
Flush PCML TX FIFO (FPLTF): When this bit is written by 1, PCML TX FIFO is flushed.
15
Flush PCMR TX FIFO (FPRTF): When this bit is written by 1, PCMR TX FIFO is flushed. 0
14
Flush Line1 TX FIFO (FL1TF): When this bit is written by 1, Line1 TX FIFO is flushed.
13
Flush PCMC TX FIFO (FPCTF): When this bit is written by 1, PCMC TX FIFO is flushed. 0
12
Flush PCML Surround TX FIFO (FPLSTF): When this bit is written by 1, PCMLS TX
FIFO is flushed.
11
Flush PCMR Surround TX FIFO (FPRSTF): When this bit is written by 1, PCMRS TX
FIFO is flushed.
10
Flush PCM LFE TX FIFO (FPLETF): When this bit is written by 1, PCMLFE TX FIFO is
flushed.
9
Flush Line2 TX FIFO (FL2TF): When this bit is written by 1, Line 2 TX FIFO is flushed.
8
Flush HSET TX FIFO (FHTF): When this bit is written by 1, HSET TX FIFO is flushed.
7
Flush IO CTRL TX FIFO (FIOCTF): When this bit is written by 1, IO CTRL TX FIFO is
flushed.
6
Flush PCML RX FIFO (FPLRF): When this bit is written by 1, PCML RX FIFO is flushed. 0
5
Flush PCMR RX FIFO (FPRRF): When this bit is written by 1, PCMR RX FIFO is flushed. 0
4
Flush Line1 RX FIFO (FL1RF): When this bit is written by 1, Line 1 RX FIFO is flushed.
3
Flush MIC RX FIFO (FMRF): When this bit is written by 1, MIC RX FIFO is flushed.
2
Flush Line2 RX FIFO (FL2RF): When this bit is written by 1, Line 2 RX FIFO is flushed.
1
Flush HSET RX FIFO (FHRF): When this bit is written by 1, HSET RX FIFO is flushed.
0
Flush IO STATUS RX FIFO (FIOSRF): When this bit is written by 1, IO Status RX FIFO is
flushed.
Note: Once bit 21 or 22 is set, PCML and PCMR FIFO will be accessed through PCML register
with interleaving method.
Rev. 3.0, 03/01, page 214 of 390
Default
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Advertisement
Table of Contents
