Nimr: Interrupt Mask Register - Hitachi HD64465 User Manual

8.4

NIMR: Interrupt Mask Register

The NIMR, a 16-bit register, serves to mask interrupt requests from the internal modules of PS/2,
PCMCIA, AFE, GPIO, Timer, KBC, IrDA, UART, PP, SCDI, USB, and ADC. This register is
initialized to H'0000 at RESET.
Address: H'10005002
Bit 15
Bit Name PS2KBM PCC0M
Initial Value 0
R/W R/W
Bit 7
Bit Name PS2MS
Initial Value 0
R/W R/W
Bit Description
15 PS2 Keyboard Interrupt Mask Control (PS2KBM)
This bit is used to control the mask option for PS2 Keyboard interrupt request.
1: The interrupt request from PS2 Keyboard is masked.
0: The interrupt request from PS2 Keyboard is not masked.
14 PCMCIA0 Interrupt Mask Control (PCC0M)
This bit is used to control the mask option for PCMCIA0 interrupt request.
1: The interrupt request from PCMCIA0 is masked.
0: The interrupt request from PCMCIA0 is not masked.
13 PCMCIA1 Interrupt Mask Control (PCC1M)
This bit is used to control the mask option for PCMCIA1 interrupt request.
1: The interrupt request from PCMCIA1 is masked.
0: The interrupt request from PCMCIA1 is not masked.
12 AFE Interrupt Mask Control (AFEM)
This bit is used to control the mask option for AFE interrupt request.
1: The interrupt request from AFE is masked.
0: The interrupt request from AFE is not masked.
11 GPIO Interrupt Mask Control (GPIOM)
This bit is used to control the mask option for GPIO interrupt request.
1: The interrupt request from GPIO is masked.
0: The interrupt request from GPIO is not masked.
Rev. 3.0, 03/01, page 84 of 390
14 13 12
PCC1M AFEM
0 0 0
R/W R/W R/W
6 5 4
IRDAM UART0M -
0 0 -
R/W R/W -
11 10 9
GPIOM TMU0M TMU1M
0 0 0
R/W R/W R/W
3 2 1
PPM SCDIM USBM
0 0 0
R/W R/W R/W
8
KBCM
0
R/W
0
ADCM
0
R/W
Default
0
0
0
0
0