Function Description; Internal Bus Interface; Clock Generator - Hitachi HD64465 User Manual

Slot Request Active Register (SRAR) [cont'd]
Bit Description
5 Slot Request 5 Active (SL5RA):
When this bit is set to 1, slot 5 request is high active.
Otherwise, slot 5 request is low active.
4 Slot Request 4 Active (SL4RA):
When this bit is set to 1, slot 4 request is high active.
Otherwise, slot 4 request is low active.
3 Slot Request 3 Active (SL3RA):
When this bit is set to 1, slot 3 request is high active.
Otherwise, slot 3 request is low active.
2 - 0 Reserved
14.3

Function Description

This Serial CODEC Interface incorporates Internal Bus Interface, Clock generator, CS42xx
Transmit/Receive data controller, AC97 Transmit/Receive data controller, and miscellaneous
function block. Each function block is described in the following sections.
14.3.1

Internal Bus Interface

This function block provides the registers that can read/write by system via an internal bus. These
registers include control registers, status registers and TX/RX data registers. These registers are
described in Section 14-2.
14.3.2

Clock Generator

This function block provides a variable frequency master clock generator and a gating CKIO
circuit. The master clock generator supports a master clock for CS4218 CODEC to allow the
CODEC have a sample rate from 8KHz to 48KHz. The frequency can be controlled by FSR
register. And the serial clock, which has half frequency of master clock, is generated in this
generator, too. The gating CKIO circuit gates CKIO in STANDBY mode to reduce power
consumption.
Rev. 3.0, 03/01, page 217 of 390
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