Figure 20.3 Crystal/Oscillator And Pll Settle Timing Diagrams; Figure 20.4 I/O Port Interrupt Timing (Falling Edge Trigger) - Hitachi HD64465 User Manual

*Power-On Reset
AFECK, UCK
PLL1, PLL2
RESET#
RESETPO#
*Crystal Standby
AFECK, UCK
AFEOSC, UCKOSC
*PLL Standby
PLL1, PLL2
PLL1SB, PLL2SB

Figure 20.3 Crystal/Oscillator and PLL Settle Timing Diagrams

A [ 25 : 1 ]
GPIO pin
( Interrupt )
IRQ0#

Figure 20.4 I/O Port Interrupt Timing (Falling Edge Trigger)

t
OSC
t
PLL
t
PxQDF
t
PORST
t
OSC
t
PLL
Rev. 3.0, 03/01, page 355 of 390