Status Register (Sr) - Hitachi HD64465 User Manual

Control Register (CR) [cont'd]
Bit Description
6 Mode Select: (MS): ( for CS4218 or CS4271)
1:the serial CODEC interface is master.
0:the serial CODEC interface is slave.
MS must be 1 for CS4271
5 Start Transfer (ST): ( for SM3-slave mode or AC97): Writing 1 to this bit will start
transmitting or receiving data. Writing 0 has no meaning.
This bit is always read 0.
4 Continue Run Enable (CRE): ( for SM3-slave mode or AC97)
1: SSYNC continues to be generated after transfer starts
0: SSYNC generation is not to be continued.
3 Flush TX FIFO (FTF): Setting this bit will flush TX FIFO, and resets the TX FIFO pointer.
Always read 0.
2 TX Enable (TXEN)
1: Enables TX done interrupt and the control of transmit data path.
0: Disabled
1 Flush RX FIFO (FRF): Setting this bit will flush RX FIFO, and reset the RX FIFO pointer.
Always read 0.
0 RX Enable(RXEN)
1: Enables RX done interrupt and the control of receive data path.
0: Disabled
14.2.4

Status Register (SR)

SR is a 16-bit Read only register that is used to reflect the status of this Serial CODEC Interface
when the CODEC is CS4271 or CS4218. If the CODEC is AC97 CODEC, this register has no
meaning. Bit 15 and bits 7 - 6 of this register are reserved. The other bits of this register are
initialized to 0 at reset. SR is not initialized in STANDBY mode.
Bit 15
Bit Name reserved IR71
Initial Value 0
R/W -
Bit 7
Bit Name reserved reserved RNE
Initial Value 0
R/W -
14 13 12
TNF TFS1
0 1 0
R R R
6 5 4
RFS1
0 0 0
- R R
11 10 9
TFS0 TFU TFO
0 0 0
R R R
3 2 1
RFS0 RFU RFO
0 0 0
R R R
Rev. 3.0, 03/01, page 187 of 390
Default
0
0
0
0
0
0
0
8
TDI
0
R
0
RDI
0
R