Hitachi HD64465 User Manual page 197

Windows ce intelligent peripheral controller
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(10) Extended Control Register (ECR) (Address H'1000A014, Mode All)
Address: H'1000A014, Mode All
Bit
7
Bit Name
MODEB2 MODEB1 MODEB0
Initial Value
0
R/W
R/W
Bit
Description
7 - 5
Mode: These bits are used for READ/WRITE and Mode selection.
4
NerrIntrEn:
1: Disables the interrupt generated on the asserting edge of the nFault input.
0: Enables the interrupt pulse on the asserting edge of the nFault. An interrupt pulse will
be generated if nFault is asserted, or if this bit is written from one to zero in the low
level nFault
3
Reserved.
2
ServiceIntr:
1: Disables all service interrupts.
0: Enables the service interrupts. This bit will be set to "1" by hardware when one of the
three service interrupts has occurred. Writing "1" to this bit will not generate an
interrupt.
1
Full
1: The FIFO is full and cannot accept another byte.
0: The FIFO has one free data byte space at least.
0
Empty
1: The FIFO is empty.
0: The FIFO contains at least one data byte.
(11) Mode Switching Operation
In programmed I/O control (mode 000 or 001), P1284 negotiation and all other tasks happening
before data is transferred, and are controlled by software. Setting mode to 011 or 010 will cause the
hardware to perform an automatic control-line handshaking, and transfer information between
FIFO and the ECP port.
From mode 000 or 001, any other mode may be immediately switched to or from the other mode.
To change direction, the mode must first be set to 001.
In extended forward mode, FIFO must be cleared and all signals deasserted before returning to
mode 000 or 001. In ECP reverse mode, all data must be read from the FIFO before returning to
mode 000 or 001. Discarded data is usually accumulated during ECP reverse handshaking, as when
mode changed during a data transfer. If the above condition is satisfied, nAutoFd will be
deasserted regardless of the transfer state. To avoid bugs during handshaking signals, the
guidelines above must be followed.
Rev. 3.0, 03/01, page 178 of 390
6
5
4
nErrIntrEn
0
0
1
R/W
R/W
R/W
3
2
1
Reserved
Full
ServiceIntr
0
1
1
R/W
R/W
R/W
0
Empty
0
R/W
Default
0
1
0
1
0
1

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