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ULSR (READ/WRITE) [cont'd]
Bit
Description
2
Indicates the parity error (PE) with a logic 1 indicating that the received data character
does not have the correct even or odd parity, as selected by ULCR(4). It will be reset to
"0" whenever the ULSR is read by the CPU.
1
Overrun Error (OE) bit which indicates by a logic 1 that the URBR has been overwritten by
the next character before it had been read by the CPU. In the FIFO mode, the OE occurs
when the FIFO is full and the next character has been completely received by the Shift
Register. It will be reset when the SR is read by CPU.
0
Data Ready (DR) bit logic "1", which indicates a character has been received by URBR,
and logic "0" indicating all of the data in URBR or RCV FIFO has been read.
Table 12.5 Line Status Register Bits
LSR Bits
LSR(7) PE/FE/BI (FIFO mode)
LSR(6) Transmitter Empty(TEMT)
LSR(5) Transmitter Holding Register Empty(THRE)
LSR(4) Break Interrupt(BI)
LSR(3) Framing Error(FE)
LSR(2) Parity Error(PE)
LSR(1) Overrun Error(OE)
LSR(0) Data Ready(DR)
Logic 1
Logic 0
Error
No error
Empty
Not empty
Empty
Not empty
Break
No break
Error
No error
Error
No error
Error
No error
Ready
Not ready
Rev. 3.0, 03/01, page 165 of 390
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