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11.3
FIR Transmit Operation
T1: Setup Phase:
(1) Set up Tx Control Registers for Transmitting options.
a. Set DCS[1:0] in IMISCR to select DMA channel for Transmit. (Set 80h to IMISCR)
b. Set SIP[1:0] and NSFP in ITC2R to send a SIR Interaction Pulse and decide the number
of starting flags or preamble. (Set 58h to ITC2R)
c. Set RSTC[3:0] in IRSTCR to reset Tx FIFO pointer. (Set 60h to IRSTCR)
d. Set BKSEL[4:0] to select Bank 2 register. (Set 02h to IMSTCR)
e. Set IRMOD[3:0] and IRSPD[3:0] in IIRC1R to specify the modulation rate. (Set 04h to
IIRC1R)
(2) Load the byte count to the Tx Byte Count Register.
a. Set BKSEL[4:0] to select Bank 1 register. (Set 01h to IMSTCR)
b. Write the transmit byte counts into ITBCLR and ITBCHR.
(3) Set up the host DMA controller channel 0 and the Tx packet.
(4) Set RTS and Transmitter Enable bits.
a. Set IEN, TXEN and BKSEL[4:0] in IMSTCR to enable FIR interrupt, Transmitter and
select bank 0. (Set c0h to IMSTCR)
b. Set RTS, TFRIEN, TFUIEN, TFTL, ADRTS, TIDL and UA in ITC1R to start to
transmit data. RTS is used to activate the REQUEST TO SEND and start transmission.
TFRIEN enables Tx FIFO Ready interrupt request, TFUIEN enables Tx FIFO
underrun/EOM interrupt request and TFTL controls Tx FIFO Threshold level. ADRTS
automatically deactives the REQUEST TO SEND, TIDL controls Tx Idle state and UA
specifies the FIFO underrun sequence. (Set fbh to ITC1R)
T2: Startup Phase:
(1) RTS is active. If no carrier is detected (Rx doesn't receive data), then the transmitter begins
to transmit.
(2) DMA request is activated if DMA is enabled. The Tx FIFO is being filled with transmitted
data. If DMA is not enabled, Write Tx FIFO command can be used. (Write data to ITFR)
(3) If the NSFP bit in ITC2R is 0, the transmitter starts sending start flags (1M) or Preambles
(4M) until the Tx FIFO is half filled (8 bytes). If the NSFP bit is 1, the transmitter waits
until the Tx FIFO is half filled, then sends two (2) start flags (1M mode) or preambles and
one (1) Start Flag (4M mode).
T3: Data Send Phase:
(1) The transmitter starts sending data stored in the FIFO.
(2) DMA request to the host is active when FIFO is not full.
Rev. 3.0, 03/01, page 153 of 390
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