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Control Register (CTR) [cont'd]
Bit
Description
5
Receive Error Interrupt (RERI) enable
1: enable
0: disable
4
Transmit Data Empty Interrupt (TDEI) enable
1: enable
0: disable
3
Receive Data Full Interrupt (RDFI) enable
1: enable
0: disable
2
Buffer Disable
1: data is transferred with register (TXDB and RXDB).
0: data is transferred with buffers (TXDB and RXDB).
1
Transmit Enable
1: enable
0: disable
0
Receive enable.
1: enable
0: disable
15.2.2
Status Register (STR)
STR, a 6-bit READ only register (0s can only be written to lower four bits for clearing after 1s are
read), indicates the status of an AFE interface. STR is not initialized in the STANDBY mode. STR
must be read in word. The valid values cannot be guaranteed after a byte read is performed.
Bit
15
Bit Name
TAB
Initial Value
0
R/W
R/(W)
Bit
7
Bit Name
reserved reserved reserved reserved TERR
Initial Value
0
R/W
R
14
13
12
RAB
reserved reserved reserved reserved reserved reserved
0
0
0
R/(W)
R
R
6
5
4
0
0
0
R
R
R
11
10
9
0
0
0
R
R
R
3
2
1
RERR
TDE
0
0
1
R/(W)
R/(W)
R/(W)
Rev. 3.0, 03/01, page 233 of 390
Default
0
0
0
0
0
0
8
0
R
0
RDF
0
R/(W)
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